From x86 architectural roots through Pentium and modern multi-core giants.
i386
3rd gen Intel architecture. It was a ground-breaking revolution at the time; It both allowed 32-bit programs to run, but...
i386
3rd gen Intel architecture.
It was a ground-breaking revolution at the time;
It both allowed 32-bit programs to run, but was also much faster than the previous-gen 286 chips at executing 16-bit (DOS) programs.
The first Intel 32-bit processor introduced in 1985.
optional separate 387 chip for FPU / floating point unit had to be purchased separately both for SX and DX series.
optional cache chip on the mainboard had to be purchased separately.
The VGA cards on those systems also had very little memory, which limited the 2D resolution
to a very low value like 640x480 or even 320x240 on some PCs, at 256-colors.
Bus was running at CPU speed, so 16-33 MHz typical.
| Specification | Value |
|---|---|
| Introduced | 1985 |
| Arch Generation | 3 |
| Core Generation | pre-historic. |
| Architecture / Codename | i386 |
| Cores / Threads | 1/1 |
| Technology Node | 1500 nm |
| Die Size | 104 mm² |
| Transistors | 275,000 |
| Frequency | 12.5-33 MHz; 16 MHz and 20 MHz were common. |
| Instructions | x86. 32-bit. |
| TDP | ~8 Watts est. |
| Cache L1 | none |
| Cache L2 | none (8 KB optional on mainboard; called "external cache") |
| Memory Type | FPM-DRAM / EDO-DRAM |
| Memory Bandwidth | |
| Memory Size Typical | 2-8 MB (and around 256K-512K video memory; limiting VGA resolution) |
| Memory Size Max | |
| Data Width 386Dx 32 Bits (386Sx | 16 bits) |
| Address Width 386Dx 32 Bits (386Sx | 24 bits) |
P4
4th gen Intel architecture. a 32-bit processor introduced in 1989. This processor contains a new x87 FPU + L1 cache. And...
📊 Benchmark Results (1)P4
4th gen Intel architecture.
a 32-bit processor introduced in 1989.
This processor contains a new x87 FPU + L1 cache. And a 33 MHz bus.
This chip, while high-end at the time, used on desktop PCs,
it could be passively cooled.
it used 5 volts (vs modern CPUs of ~0.7-1.0 V).
486 was about 2x (twice) as fast as a 386 at the same clock rate !
So a 486DX2-66 was about ~8x times (!) faster than a 386DX-16 chip in most 16-bit and 32-bit applications.
2x due to IPC; instructions per clock efficiency gains of 486 architecture.
multiplied by 4x due to higher clock-rate. All that in a space of only several years !
Mind-boggling progress at the time in the 1980's and the 1990's. The Golden Era of Compute.
486SX - a variant without a floating-point unit (FPU), which had to be purchased separately.
486DX-33 MHz - multiplier x1; released in 1989.
486DX2-66 MHz - multiplier x2; released in 1992. (most common)
486DX4-100 MHz - multiplier x3 (not x4 !); released in 1994 + 16K L1 cache. 1.6m transistors.
There were also a variants with 20 MHz/40/50 and 75 MHz. Less common.
1 result(s) recorded for this family.
Flagship: Intel 486DX2-66 MHz
ST score/GHz: 36.2 · MT score/Watt: 0.34
| Specification | Value |
|---|---|
| Introduced | 1989 |
| Arch Generation | 4 |
| Core Generation | pre-historic. |
| Architecture / Codename | P4 |
| Cores / Threads | 1/1 |
| Technology Node | 800 nm (600 nm for some models) |
| Die Size | ~90 mm² |
| Transistors | 1.25 million |
| Frequency | 33-100 MHz |
| Instructions | 8 KB (shared for i+d) |
| TDP | ~10 Watts est. |
| Cache L2 | up to 512 KB (on mainboard) |
| Memory Type | EDO-DRAM (most common) |
| Memory Bandwidth | |
| Memory Size Typical | 8-16 MB |
| Memory Size Max | theoretical. max = 4 GB; practical max = 64 MB |
| Note | After Intel, other vendors, including AMD, Cyrix, GreenCPU, IBM and ST copied this design, and released their own compatible versions. They had very similar architecture and performance, and were socket compatible with Intel systems. |
P5 aka i586 / P54C
5th gen Intel architecture. Pentium era. First Super-scalar architecture, when a CPU can execute up-to 2 cycles per seco...
📊 Benchmark Results (2)P5 aka i586 / P54C
5th gen Intel architecture. Pentium era.
First Super-scalar architecture, when a CPU can execute up-to 2 cycles per second,
assuming they don't have dependency on each other. The CPU decoder and issuer
can dispatch and execute commands in parallel.
While other vendors could copy and clone Intel 386/486 chips due to Intel agreement with IBM, nobody
could clone the Pentium, meaning that the competition had to develop a new architecture from the ground-up.
Pentium 66-200 MHz.
2 result(s) recorded for this family.
Flagship: Intel Pentium 100 MHz
ST score/GHz: 118 · MT score/Watt: 1.18
| Specification | Value |
|---|---|
| Introduced | 1993 |
| Arch Generation | 5 |
| Core Generation | pre-historic. |
| Architecture / Codename | P5 aka i586 / P54C |
| Cores / Threads | 1/1 |
| Technology Node | 800 nm (P5) (600 nm and 350 nm for newer models) |
| Die Size | ??? mm^2 |
| Transistors | 3.1 million |
| Frequency | 66-200 MHz |
| Instructions | 16 KB (8+8) |
| TDP | ~10? Watts |
| Socket | Socket 7 (also in Super-Socket 7) |
| Cache L2 | up to 1 MB (on mainboard) |
| Memory Type | EDO-DRAM or SDRAM (on some models) |
| Memory Bandwidth | |
| Memory Size Typical | 8-16 MB |
| Memory Size Max | theoretical. max = 4 GB. |
P55C aka i586
Adds MMX technology and double L1 cache memory....
📊 Benchmark Results (3)P55C aka i586
Adds MMX technology and double L1 cache memory.
Pentium MMX 166-233 MHz on desktoplis. Some mobile versions could go even as high as 300 MHz.
3 result(s) recorded for this family.
Flagship: Intel Pentium 200 MHz MMX
ST score/GHz: 119 · MT score/Watt: 1.49
| Specification | Value |
|---|---|
| Introduced | 1997 |
| Arch Generation | 5.5 |
| Core Generation | pre-historic. |
| Architecture / Codename | P55C aka i586 |
| Cores / Threads | 1/1 |
| Technology Node | 280 nm (P55C) |
| Die Size | ??? mm^2 |
| Transistors | 4.5 million |
| Frequency | 166-233 MHz |
| Instructions | 32 KB (16+16) |
| TDP | ~13-17 Watts |
| Socket | Socket 7 (also in Super-Socket 7) |
| Cache L2 | up to 1 MB (on mainboard) |
| Memory Type | EDO-DRAM or SDRAM (on some models) |
| Memory Bandwidth | |
| Memory Size Typical | 16-32 MB |
| Memory Size Max | theoretical. max = 4 GB. |
P6 (Klamath and Deschutes)
the Pentium II. Revolutionary P6 architecture. Super-scalar with multiple execution units, branch prediction and micro-c...
📊 Benchmark Results (8)P6 (Klamath and Deschutes)
the Pentium II. Revolutionary P6 architecture.
Super-scalar with multiple execution units, branch prediction and micro-code
to transform x86 to internal machine-code.
Much faster than the original Pentium, clock-for-clock on 32-bit code execution.
Speculative execution and out-of-order completion.
All modern processors are essentially based on this concept, so we can call all
modern CPUs as a Pentium II-descendats of sorts, at least in idea.
L2 cache works at half the CPU speed, so a 400 MHz chip had only a 200 MHz L2 cache.
L1 cache always works at full CPU speed, for all models.
Celeron, based on the Pentium II, had no L2 cache at all for early models, and only 128 KB
for later models; while Server-based Pentium II Xeon chips have had 1 MB or 2 MB full-speed L2.
8 result(s) recorded for this family.
Flagship: Intel Pentium II 400 MHz
ST score/GHz: 231 · MT score/Watt: 3.86
| Specification | Value |
|---|---|
| Introduced | 1997 |
| Arch Generation | 6 |
| Core Generation | pre-historic. |
| Architecture / Codename | P6 (Klamath and Deschutes) |
| Cores / Threads | 1/1 |
| Technology Node | 250 nm (250 for Deschutes and 350 nm for Klamath) |
| Die Size | 113 mm² (for Deschutes); and bigger for Klamath |
| Transistors | 7.5 million |
| Frequency | 233-450 MHz |
| Instructions | 16 KB / 16 KB |
| TDP | ~15-30? Watts |
| Socket | Slot 1 |
| Cache L2 | 512 KB; at half-speed. |
| Memory Type | SDRAM-100 |
| Memory Bandwidth | 1 GB/s |
| Memory Size Max | 4 GB (theoretical; or 64 GB in PAE mode) |
| Memory Size Typical | 64-128 MB |
P6
Evolution of the Pentium II. Same P6 architecture, same slot 1, but adds SSE instructions to accelerate 3D gaming. L2 ca...
📊 Benchmark Results (4)P6
Evolution of the Pentium II. Same P6 architecture, same slot 1, but adds SSE instructions to accelerate 3D gaming.
L2 cache works at half the CPU speed.
4 result(s) recorded for this family.
Flagship: Intel Pentium III 600 MHz
ST score/GHz: 228 · MT score/Watt: 4.03
| Specification | Value |
|---|---|
| Introduced | 1999 |
| Arch Generation | 6 |
| Core Generation | pre-historic. |
| Architecture / Codename | P6 |
| Cores / Threads | 1/1 |
| Technology Node | 250 nm |
| Die Size | 128 mm² |
| Transistors | 9.5 million |
| Frequency | 450-600 MHz |
| Instructions | 16 KB / 16 KB |
| TDP | ~30? Watts |
| Socket | Slot 1 |
| Cache L2 | 512 KB; at half-speed. |
| Memory Type | SDRAM-100 / SDRAM-133 |
| Memory Bandwidth | 1 GB/s |
| Memory Size Max | 4 GB (theoretical; or 64 GB in PAE mode) |
| Memory Size Typical | 64-128 MB |
P6
Pentium III "Coppermine" converts the slot-based into socket-based system. Plus adds 256 KB of L2-cache at ful...
📊 Benchmark Results (7)P6
Pentium III "Coppermine" converts the slot-based into socket-based system.
Plus adds 256 KB of L2-cache at full CPU speed. And bus speed upgrade to 133 MHz.
Also shrinks the node process from 250 to 180 nm, doubling the performance.
transistor count tripled due to the on-chip L2 cache.
7 result(s) recorded for this family.
Flagship: Intel Pentium III 1000 MHz
ST score/GHz: 262 · MT score/Watt: 9.03
| Specification | Value |
|---|---|
| Introduced | 1999 |
| Arch Generation | 6 |
| Core Generation | pre-historic. |
| Architecture / Codename | P6 |
| Cores / Threads | 1/1 |
| Technology Node | 180 nm |
| Die Size | 80 mm² |
| Transistors | 28 million |
| Frequency | 500-1133 MHz |
| Instructions | 16 KB / 16 KB |
| TDP | ~30? Watts |
| Socket | Socket 370 |
| Cache L2 | 256 KB; at full-speed. |
| Memory Type | SDRAM-133 |
| Memory Bandwidth | 1 GB/s |
| Memory Size Max | 4 GB (theoretical; or 64 GB in PAE mode) |
| Memory Size Typical | 64-256 MB |
Yonah
Last gen of 32-bit processor architecture. Direct descendent of the Pentium M "Centrino". The only 32-bit proc...
📊 Benchmark Results (1)Yonah
Last gen of 32-bit processor architecture. Direct descendent of the Pentium M "Centrino".
The only 32-bit processor in the world, that also supports hardware vitualization, VT-x.
Core Solo -- a single-core version also exists.
1 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) Duo CPU T2600 @ 2.16GHz
ST score/GHz: 331 · MT score/Watt: 46.2
| Specification | Value |
|---|---|
| Introduced | 2005 |
| Arch Generation | 7 |
| Core Generation | 0 |
| Architecture / Codename | Yonah |
| Cores / Threads | 2/2 |
| Technology Node | 65 nm |
| Die Size | 90 mm² |
| Transistors | 151 million |
| Frequency | 1600-2333 MHz |
| Instructions | (64 KB / core) (32 KB + 32 KB) |
| TDP | ~30 Watts |
| Socket | Socket 479 |
| Cache L2 | 2 MB total; 1 MB / core |
| Memory Type | DDR1 SDRAM |
| Memory Bandwidth | |
| Memory Size Typical | 1-2 GB |
| Memory Size Max | 4 GB (for most common mainboards) |
NetBust / Willamette
Pentium 4 is the next-gen of Intel Architecture. In an attempt to increase clock-speeds even faster, Intel has designed ...
NetBust / Willamette
Pentium 4 is the next-gen of Intel Architecture.
In an attempt to increase clock-speeds even faster, Intel has designed a new CPU architecture
from the ground-up, with very long pipeline.
It performed well in some workloads including multimedia / video encoding and de-coding, but
it did poorly with unpredictable code patterns, especially emulation, even slower than the older Pentium III and AMD Athlon in many workloads.
Because of the long pipeline, Instructions per cycle (IPC), was the lowest in the industry, much under-performing vs.
both the Pentium III and the Pentium 4.
Longer pipelines allows to increase the clock speed, at the cost of power consumption, branch mispredicts and data cache misses, resulting in lower IPC.
Intel hoped it would reach up to 10 GHz and above, but it never did.
It was a very power hungry design, unstable to scale, and it did very poorly in laptop-designs.
Eventually after reaching over 3 GHz, intel realized that the architecture is simply inefficient,
they abandoned it and replaced it with a Core 2 Duo architecture, based on the Pentium III, not the Pentium 4 !
Initially it required a very pricey and expensive RDRAM memory, limiting user's appeal, but later
it migrated to SDRAM and DDR memory standards.
| Specification | Value |
|---|---|
| Introduced | 2000 |
| Arch Generation | 7 |
| Core Generation | pre-historic. |
| Architecture / Codename | NetBust / Willamette |
| Cores / Threads | 1/1 |
| Technology Node | 180 nm |
| Die Size | 217 mm^2 |
| Transistors | 42 million |
| Frequency | 1300-2000 MHz |
| Instructions | 8 KB / 8 KB (8 KB for micro-instructions t-cache) |
| TDP | ~35-110 Watts |
| Socket | Socket 423 |
| Cache L2 | 256 KB |
| Memory Type | SDRAM/DDR1/DDR2/RDRAM |
| Memory Bandwidth | varied. |
| Memory Size Max | 4 GB (64 GB with PAE mode) |
| Memory Size Typical | 64-128 MB; mainly because early models with RDRAM were crazy expensive. |
NetBust / Northwood
Northwood was a 2nd-gen Pentium 4, upgrading sockets, and doubling the L2 cache to 512 KB, tech node from 180 to 130 nm,...
📊 Benchmark Results (1)NetBust / Northwood
Northwood was a 2nd-gen Pentium 4, upgrading sockets, and doubling the L2 cache to 512 KB,
tech node from 180 to 130 nm, and improving clock rate and performance significantly.
Some models even support Hyper-threading, allowind for 2 threads on a single-core.
The idea is that for a +5% transistor budget, it is possible to get a +30% performance in some applications.
Increased transistor budget from 42 to 55 million comes mainly from the doubling of L2 cache.
1 result(s) recorded for this family.
Flagship: Intel(R) Pentium(R) 4 CPU 2.80GHz
ST score/GHz: 220 · MT score/Watt: 8.94
| Specification | Value |
|---|---|
| Introduced | 2002 |
| Arch Generation | 7 |
| Core Generation | pre-historic. |
| Architecture / Codename | NetBust / Northwood |
| Cores / Threads | 1/2 |
| Technology Node | 130 nm |
| Die Size | 131 mm^2 |
| Transistors | 55 million |
| Frequency | 1600-3400 MHz |
| Instructions | 8 KB / 8 KB (8 KB for micro-instructions t-cache) |
| TDP | ~35-110 Watts |
| Socket | Socket 478 |
| Cache L2 | 512 KB |
| Memory Type | SDRAM/DDR1/DDR2/RDRAM |
| Memory Bandwidth | varied. |
| Memory Size Max | 4 GB (64 GB with PAE mode) |
| Memory Size Typical | 128-512 MB (typically with a much cheaper DDR1 SDRAM) |
Banias / Dothan / Centrino
Pentium M is an alternative upgrade-path as the next-gen of Intel Architecture, instead of the Pentium 4. Based on the P...
📊 Benchmark Results (8)Banias / Dothan / Centrino
Pentium M is an alternative upgrade-path as the next-gen of Intel Architecture, instead of the Pentium 4.
Based on the Pentium III, it extends the arch with new instructions (SSE2),
new bus, improved branch prediction and bigger L1+ L2 caches.
Basically this works as a much improved Pentium III,
without the power-hungry problems of the Pentium 4.
It was sold mostly on laptops, marketed as an "Intel Centrino" platforms, together with a Wi-Fi chip !
Until 2003 "Centrino", most of the laptops had no Wi-Fi chip and were connected to the Internet via wired LAN RJ-45 Ethernet cable.
Basically during this age, laptops were using the Pentium M "Centrino", while desktops were using the "Pentium 4".
Totally different chips with totally different architecture and characteristics.
Compared to the Pentium 4, the Pentium M had no hyper-threading, had a much lower clock-speed, but much higher IPC (instructions-per-clock), and better power efficienty (amount of work per watt of power).
Pentium M achieved similar performance to the Pentium 4, in some workloads even out-performing it, while using only 1/3rd of the power !
At this point it became obvious, that the Pentium 4 is hitting a dead-end, and must be replaced, even on the desktop !
Pentium M, like the previous Pentium III were single-core, single-threaded design running 32-bit x86 code.
Dothan is a 2nd-gen Pentium M, doubles transistors and L2 cache, and reduces node to 90 nm, introduced in 2004.
8 result(s) recorded for this family.
Flagship: Intel(R) Pentium(R) M processor 1.80GHz
ST score/GHz: 312 · MT score/Watt: 26.7
| Specification | Value |
|---|---|
| Introduced | 2003 |
| Arch Generation | 7 |
| Core Generation | pre-historic. |
| Architecture / Codename | Banias / Dothan / Centrino |
| Cores / Threads | 1/1 |
| Technology Node | 130 nm for Banias; 90 nm for Dothan |
| Die Size | 83 mm^2 for Banias; 87 mm^2 for Dothan. |
| Transistors | 77 million for Banias; 140 million for Dothan. |
| Frequency | 1300-2000+ MHz |
| Instructions | 32 KB / 32 KB (64 KB) |
| TDP | ~20-30 Watts |
| Socket | Socket 479 |
| Cache L2 | 1 MB for Banias; 2 MB for Dothan. |
| Memory Type | DDR1 |
| Memory Bandwidth | |
| Memory Size Max | 2 GB |
| Memory Size Typical | 256-2048 MB |
Conroe
Conroe. The next-gen of Intel Architecture. First Intel processor to fix the short-comings of an ultra-long Pentium 4 pi...
📊 Benchmark Results (5)Conroe
Conroe. The next-gen of Intel Architecture.
First Intel processor to fix the short-comings of an ultra-long Pentium 4 pipeline.
this pipeline was both slow for many workloads, and power-hungry.
This is a evolution of the Pentium III (and Pentium M), while discardind the Pentium 4
architecture.
Core 2 Quad Q6000 series "Kentsfield" have 4-cores. Double the cores, transistors and the TDP to 130 Watts.
Some models have halved L2 cache, and/or disabled VT-x virtualization.
5 result(s) recorded for this family.
Flagship: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz
ST score/GHz: 409 · MT score/Watt: 30.2
| Specification | Value |
|---|---|
| Introduced | 2006 |
| Arch Generation | 8 (8.1) |
| Core Generation | 0 |
| Architecture / Codename | Conroe |
| Cores / Threads | 2/2 |
| Technology Node | 65 nm |
| Die Size | 143 mm^2 (much less for 2 MB versions; E6300 and E6400) |
| Transistors | 291 million (much less for 2 MB versions; E6300 and E6400) |
| Frequency | 1866-2933 MHz |
| Instructions | (64 KB / core) (32 KB + 32 KB) |
| TDP | 65 Watts |
| Socket | Socket 775 |
| Cache L2 | 4 MB total; 2 MB / core |
| Memory Type | DDR2/DDR3 SDRAM |
| Memory Bandwidth | 25.6 GB/s |
| Memory Size Typical | 1-4 GB |
| Memory Size Max | 8 GB (for most common mainboards) |
Wolfdale
Wolfdale. An improved Conroe. Much smaller process node leads to a much smaller die size. Intel decided to increase cach...
📊 Benchmark Results (6)Wolfdale
Wolfdale. An improved Conroe.
Much smaller process node leads to a much smaller die size.
Intel decided to increase cache size from 4 MB to 6 MB. By +50%.
Intel also improved branch prediction, added a Radix-16 divider,
improving performance and introduced SSE 4.1 new instructions.
Core 2 Quad Q8000/ Q9000 series "Yorkfield" have 4-cores. Double the cores, transistors and the TDP to 130 Watts.
Some models have halved L2 cache, and/or disabled VT-x virtualization.
6 result(s) recorded for this family.
Flagship: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz
ST score/GHz: 436 · MT score/Watt: 40.2
| Specification | Value |
|---|---|
| Introduced | 2007 |
| Arch Generation | 8 (8.2) |
| Core Generation | 0 |
| Architecture / Codename | Wolfdale |
| Cores / Threads | 2/2 |
| Technology Node | 45 nm |
| Die Size | 107 mm^2 |
| Transistors | 410 million |
| Frequency | 2533-3500 MHz |
| Instructions | (64 KB / core) (32 KB + 32 KB) |
| TDP | 65 Watts |
| Socket | Socket 775 |
| Cache L2 | 6 MB total; 3 MB / core |
| Memory Type | DDR2/DDR3 SDRAM |
| Memory Bandwidth | 25.6 GB/s |
| Memory Size Typical | 1-4 GB |
| Memory Size Max | 8 GB (for most common mainboards) |
Nehalem / (Bloomfield or Lynnfield)
Nehalem. The next-gen of Intel Architecture. First Intel processor to integrate memory-controller on die, in the CPU its...
📊 Benchmark Results (1)Nehalem / (Bloomfield or Lynnfield)
Nehalem. The next-gen of Intel Architecture.
First Intel processor to integrate memory-controller on die, in the CPU itself, rather than in chipset.
Adds SSE4.2 instructions and VT-x Nested Page Tables (aka VT-x 2.0) -- much faster virtualization.
First CPU based to Intel Core to re-add the previously lost during Core 2 Duo era of "Hyper-Threading" technology.
First CPU to feature both quad-core and 8-threads ! It was a whopping *huge* deal back in 2008 !
First CPU to make DDR3 memory the common standard ! (most of previous-gen Core 2 Duos were running on DDR2)
Bloomfield has a triple-channel memory controller vs. a dual-channel memory for Lynnfield.
Performance for most applications is comparable.
1 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz
ST score/GHz: 548 · MT score/Watt: 94.9
| Specification | Value |
|---|---|
| Introduced | 2008 |
| Arch Generation | 9 |
| Core Generation | 1 |
| Architecture / Codename | Nehalem / (Bloomfield or Lynnfield) |
| Cores / Threads | 4/8 |
| Technology Node | 45 nm |
| Die Size | 263 mm² |
| Transistors | 731 million |
| Frequency | 2666-3200 MHz |
| Instructions | 4x 32 KB + 32 KB |
| TDP | 130 Watts |
| Socket | Socket 1156 for i7-860 Lynnfield; Socket 1366 for i7-920 Bloomfield. |
| Cache L2 | 4x 256 KB |
| Cache L3 | 8 MB (2MB per core, shared) |
| Cache | 9 MB |
| Memory Type | DDR3-1066 SDRAM |
| Memory Bandwidth | 25.6 GB/s |
| Memory Size Typical | 4-8 GB |
| Memory Size Max | 24 GB |
Sandy Bridge
This CPU was so much faster than Nehalem, and Intel progress were to slow down for the next-decade so much so that peopl...
📊 Benchmark Results (2)Sandy Bridge
This CPU was so much faster than Nehalem, and Intel progress were to slow down for the next-decade
so much so that people who bought this CPU made the purchase-of-the-decade !
Meaning buying one computer and no need to upgrade for a decade, because it's performance was still adequate for tasks a decade later in 2021 !
This was unheard of for people in the 90's,
when people were getting +300% performance boost was common every 3-4 years !
2 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz
ST score/GHz: 599 · MT score/Watt: 117
| Specification | Value |
|---|---|
| Introduced | Feb, 2011 |
| Arch Generation | 10 |
| Core Generation | 2 |
| Architecture / Codename | Sandy Bridge |
| Cores / Threads | 4/8 |
| Technology Node | 32 nm |
| Die Size | 216 mm² |
| Transistors | 1.16 billion |
| Frequency | 3400-3800 MHz |
| Instructions | (64 KB/core) (32 KB + 32 KB) |
| TDP | 95 Watts |
| Socket | Socket 1155 |
| Cache L2 | 256 KB / core |
| Cache L3 | 8 MB (2MB per core, shared) |
| Memory Type | DDR3 SDRAM |
| Memory Bandwidth | 21 GB/s |
| Memory Size Typical | 8-16 GB |
| Memory Size Max | 32 GB |
Ivy Bridge (Sandy Bridge variant)
A small improvement over Sandy Bridge 2000 series. Moved to a new 22 nm node. But performance is largely the same....
Ivy Bridge (Sandy Bridge variant)
A small improvement over Sandy Bridge 2000 series. Moved to a new 22 nm node.
But performance is largely the same.
| Specification | Value |
|---|---|
| Introduced | 2012 |
| Arch Generation | 10 |
| Core Generation | 3 |
| Architecture / Codename | Ivy Bridge (Sandy Bridge variant) |
| Cores / Threads | 4/8 |
| Technology Node | 22 nm |
| Die Size | 160 mm² |
| Transistors | 1.4 billion |
| Frequency | 3400-3800 MHz |
| Instructions | (64 KB/core) (32 KB + 32 KB) |
| TDP | 77 Watts |
| Socket | Socket 1155 |
| Cache L2 | 256 KB / core |
| Cache L3 | 8 MB (2MB per core, shared) |
| Memory Type | DDR3 SDRAM |
| Memory Bandwidth | 21 GB/s |
| Memory Size Typical | 8-16 GB |
| Memory Size Max | 32 GB |
Haswell
One of the biggest generations ever made by Intel in terms of new features & instructions. 2nd biggest only to AMD A...
📊 Benchmark Results (5)Haswell
One of the biggest generations ever made by Intel in terms of new features & instructions.
2nd biggest only to AMD Athlon 64 -- invention of x86-64 architecture itself !
It has added AVX2, BMI, HLE , RTM, FMA3, MOVBE, zero-latency register moves,
and more.
HLE - Hardware Lock Elision, a backward compatible set of prefixes that can be applied to instructions such as LOCK CMPXCHG to minimize lock overhead under low contention
RTM - Restricted Transactional Memory, the feature I've anticipated the most, the ability to atomically roll back a block of code or atomically commit a block of code
BMI - Bit Manipulation Instructions, this is a set of about a dozen new 32-bit and 64-bit integer operations designed to perform Hacker's Delight type of bit manipulation instructions, bitfield operations, and flag-less shifts and multiplies. These are designed to accelerate encryption and handling of non-byte aligned data, such as processing bit vectors, decoding instructions, or performing bitfield moves.
AVX2 - what SSE2 was to SSE, AVX2 is to AVX, adding 256-bit packed integer operations to the AVX instruction set
FMA3 - Fused-Multiply-Add support permits common floating operations such as dot product and matrix multiply to execute multiply+add in one instruction
a 4th ALU - up to 4 integer ALU operations can retire per clock cycle, leading to peak integer performance of over 14000 MIPS per core, definitely something that helps legacy code
MOVBE - Move Big Endian load/store support, previously only available on the Atom, specifically helps to accelerate simulators of big endian machines such as 68040 and PowerPC.
zero-latency register moves - common register-to-register move operations are handled by the register renamer instead of wasting an ALU operation, speeding up register calling convention
Read "Haswell's great leap forward":
http://emulators.com/docs/nx36_haswell_262.htm
5 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz
ST score/GHz: 735 · MT score/Watt: 167
| Specification | Value |
|---|---|
| Introduced | 2013 |
| Arch Generation | 11 |
| Core Generation | 4 |
| Architecture / Codename | Haswell |
| Cores / Threads | 4/8 |
| Technology Node | 22 nm |
| Die Size | 177 mm² |
| Transistors | 1.4 billion |
| Frequency | 3400-4400 MHz |
| Instructions | (64 KB/core) (32 KB + 32 KB) |
| TDP | 84 Watts |
| Socket | Socket 1150 |
| Cache L2 | 256 KB / core |
| Cache L3 | 8 MB (2MB per core, shared) |
| Memory Type | DDR3 SDRAM, 1600 |
| Memory Bandwidth | 25.6 GB/s |
| Memory Size Typical | 8-32 GB |
| Memory Size Max | 32 GB |
Broadwell (Haswell variant)
Broadwell was an evolution of Haswell. Moved to 14nm node process. Added ADX (arbitrary-precision integer), RDSEED (a ne...
Broadwell (Haswell variant)
Broadwell was an evolution of Haswell. Moved to 14nm node process. Added ADX (arbitrary-precision integer),
RDSEED (a new random number generator for improved security & encryption).
Note, that this generation never offered top-of-the-line desktop & gaming PC, something like the hypothetical Core i7-5700K.
This generation was mostly successful at mobile (notebook & laptop) markets with the Core i7 5600U,
and server market with Xeon E5 v4 family.
| Specification | Value |
|---|---|
| Introduced | 2014 |
| Arch Generation | 11 |
| Core Generation | 5 |
| Architecture / Codename | Broadwell (Haswell variant) |
| Cores / Threads | 2/4 |
| Technology Node | 14 nm |
| Die Size | ?? mm^2 |
| Transistors | ?? billion |
| Frequency | ? MHz |
| Instructions | (64 KB / core) (32 KB + 32 KB) |
| TDP | 15 Watts |
| Cache L2 | 256 KB / core |
| Cache L3 | 4 MB (in this dual-core chip) (2 MB per core) |
| Memory Type | DDR3 SDRAM, 1600 |
| Memory Bandwidth | 25.6 GB/s |
| Memory Size Max | 32 GB |
Skylake
Skylake. The first mass-production 14nm Intel Architecture for the desktop. Also moved to DDR4 memory, and a new socket....
📊 Benchmark Results (1)Skylake
Skylake. The first mass-production 14nm Intel Architecture for the desktop.
Also moved to DDR4 memory, and a new socket.
Performance-wise it is a slightly improved version of Haswell, only a few % faster.
1 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz
ST score/GHz: 759 · MT score/Watt: 233
| Specification | Value |
|---|---|
| Introduced | 2015 |
| Arch Generation | 12 |
| Core Generation | 6 |
| Architecture / Codename | Skylake |
| Cores / Threads | 4/8 |
| Technology Node | 14 nm |
| Die Size | ~125 mm^2 |
| Transistors | ~1.75 billion |
| Frequency | 3400-4200 MHz |
| Instructions | (64 KB/core) (32 KB + 32 KB) |
| TDP | 84 Watts |
| Socket | Socket 1151v1 |
| Cache L2 | 256 KB/core |
| Cache L3 | 8 MB (2MB per core, shared) |
| Memory Type | DDR4 SDRAM |
| Memory Bandwidth | - GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 64 GB |
Kaby Lake (Skylake variant)
Kaby Lake is a slightly improved variant of Skylake; A bit higher clocks....
📊 Benchmark Results (2)Kaby Lake (Skylake variant)
Kaby Lake is a slightly improved variant of Skylake; A bit higher clocks.
2 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i7-7700 CPU @ 3.60GHz
ST score/GHz: 783 · MT score/Watt: 251
| Specification | Value |
|---|---|
| Introduced | 2017 |
| Arch Generation | 12 |
| Core Generation | 7 |
| Architecture / Codename | Kaby Lake (Skylake variant) |
| Cores / Threads | 4/8 |
| Technology Node | 14 nm |
| Die Size | ~125 mm^2 |
| Transistors | ~1.75 billion |
| Frequency | 3400-4400 MHz |
| Instructions | (64 KB / core) (32 KB + 32 KB) |
| TDP | 84 Watts |
| Socket | Socket 1151v1 |
| Cache L2 | 256 KB / core |
| Cache L3 | 8 MB (2MB per core, shared) |
| Memory Type | DDR4 SDRAM |
| Memory Bandwidth | - GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 64 GB |
Coffee Lake (Skylake variant)
After failing to intoduce 10nm process in 2016, as planned by Intel's Tick/Tock plan, Intel got stuck with Skylake ...
📊 Benchmark Results (2)Coffee Lake (Skylake variant)
After failing to intoduce 10nm process in 2016, as planned by Intel's Tick/Tock plan, Intel got stuck with Skylake 14-nm variants for many years...
Same eggs, a different busket.
But this generation Intel decided to upgrade core count from 4 to 6, pushing performance upwards.
(also upping mobile U-variants from 2 to 4 cores. U stands for "Ultrabook")
2 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz
ST score/GHz: 783 · MT score/Watt: 307
| Specification | Value |
|---|---|
| Introduced | 2017 |
| Arch Generation | 12 |
| Core Generation | 8 |
| Architecture / Codename | Coffee Lake (Skylake variant) |
| Cores / Threads | 6/12 |
| Technology Node | 14 nm |
| Die Size | ~151 mm^2 |
| Transistors | approx. 3 billion |
| Frequency | 3400-4700 MHz |
| Instructions | (64 KB / core) (32 KB + 32 KB) |
| TDP | 95 Watts |
| Socket | Socket 1151v2 |
| Cache L2 | 256 KB / core |
| Cache L3 | 12 MB (2MB per core, shared) |
| Memory Type | DDR4-2666 SDRAM |
| Memory Bandwidth | 41.6 GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 128 GB |
Coffee Lake refresh (Skylake variant)
This generation Intel decided to upgrade core count to 8, pushing performance upwards even further. This CPU hit the 5 G...
📊 Benchmark Results (1)Coffee Lake refresh (Skylake variant)
This generation Intel decided to upgrade core count to 8, pushing performance upwards even further.
This CPU hit the 5 GHz Mark !
1 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i9-9900K CPU @ 3.60GHz
ST score/GHz: 800 · MT score/Watt: 277
| Specification | Value |
|---|---|
| Introduced | 2018 |
| Arch Generation | 12 |
| Core Generation | 9 |
| Architecture / Codename | Coffee Lake refresh (Skylake variant) |
| Cores / Threads | 8/16 |
| Technology Node | 14 nm |
| Die Size | 177 mm^2 |
| Transistors | approx ~4 billion. |
| Frequency | 3400-5000 MHz |
| Instructions | (64 KB / core) (32 KB + 32 KB) |
| TDP | 95 Watts |
| Socket | Socket 1151v2 |
| Cache L2 | 256 KB / core |
| Cache L3 | 16 MB (2MB per core, shared) |
| Memory Type | DDR4-2666 SDRAM |
| Memory Bandwidth | 41.6 GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 128 GB |
Comet Lake (Skylake variant)
This generation Intel decided to upgrade core count to 10, pushing performance upwards even further....
📊 Benchmark Results (1)Comet Lake (Skylake variant)
This generation Intel decided to upgrade core count to 10, pushing performance upwards even further.
1 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i9-10900K CPU @ 3.70GHz
ST score/GHz: 786 · MT score/Watt: 194
| Specification | Value |
|---|---|
| Introduced | 2020 |
| Arch Generation | 12 |
| Core Generation | 10 |
| Architecture / Codename | Comet Lake (Skylake variant) |
| Cores / Threads | 10/20 |
| Technology Node | 14 nm |
| Die Size | ~200 mm² |
| Transistors | approx ~5 billion. |
| Frequency | 3400-5300 MHz |
| Instructions | (64 KB / core) (32 KB + 32 KB) |
| TDP | 125 Watts |
| Socket | Socket 1200 |
| Cache L2 | 256 KB / core |
| Cache L3 | 20 MB (2MB per core, shared) |
| Memory Type | DDR4-2933 SDRAM |
| Memory Bandwidth | 45.8 GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 128 GB |
Rocket Lake / Cypress Cove / Sunny Cove
Next-gen Intel architecture after such a long time... This generation has finally added AVX512 (512-bit wide vectors) to...
📊 Benchmark Results (1)Rocket Lake / Cypress Cove / Sunny Cove
Next-gen Intel architecture after such a long time...
This generation has finally added AVX512 (512-bit wide vectors) to the Intel's desktop chips lineup.
AVX512 was subsequently removed from 12th-gen and later chips.
1 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i9-11900K @ 3.50GHz
ST score/GHz: 813 · MT score/Watt: 314
| Specification | Value |
|---|---|
| Introduced | 2021-03 |
| Arch Generation | 13 |
| Core Generation | 11 |
| Architecture / Codename | Rocket Lake / Cypress Cove / Sunny Cove |
| Cores / Threads | 8/16 |
| Technology Node | 14 nm |
| Die Size | 276 mm² |
| Transistors | approx ~7 billion. |
| Frequency | 3500-5300 MHz |
| Instructions | (80 KB / core) (32 KB + 48 KB) |
| TDP | 125 Watts |
| Socket | Socket 1200 |
| Cache L2 | 512KB / core |
| Cache L3 | 16 MB (2MB per core, shared) |
| Memory Type | DDR4-3200 SDRAM |
| Memory Bandwidth | 50 GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 128 GB |
Alder Lake / Golden Cove
Alder Lake is a next-gen Intel architecture. Finally moved to 10 nm, and it is *much* much faster than anything before i...
📊 Benchmark Results (2)Alder Lake / Golden Cove
Alder Lake is a next-gen Intel architecture. Finally moved to 10 nm, and it is *much* much faster than anything before it.
Dropped AVX512, but gained "Efficiency cores" (aka small cores), plus a much better branch prediction.
This is the 1st gen to Introduce DDR5 memory.
2 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i9-12900K
ST score/GHz: 1,277 · MT score/Watt: 333
| Specification | Value |
|---|---|
| Introduced | 2021 |
| Arch Generation | 14 |
| Core Generation | 12 |
| Architecture / Codename | Alder Lake / Golden Cove |
| Cores / Threads | 8P+8e/24 |
| Technology Node | 10 nm |
| Die Size | 215 mm² |
| Transistors | |
| Frequency | 3200-5200 MHz |
| Instructions | (80 KB / P-core) (32 KB + 48 KB) |
| TDP | 241 Watts |
| Socket | Socket 1700 |
| Cache L2 | 1.25 MB / P-core |
| Cache L3 | 30 MB (shared) |
| Memory Type | DDR4-3200 or DDR5-4800 SDRAM |
| Memory Bandwidth | 75 GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 128 GB |
Raptor Lake / Golden Cove
Raptor Lake is has similar Architecture to 12000-series "Alder Lake", but more E-cores (small / efficiency cor...
📊 Benchmark Results (1)Raptor Lake / Golden Cove
Raptor Lake is has similar Architecture to 12000-series "Alder Lake",
but more E-cores (small / efficiency cores) and higher clock speed, and more cache.
1 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i9-13900
ST score/GHz: 1,218 · MT score/Watt: 324
| Specification | Value |
|---|---|
| Introduced | 2022 |
| Arch Generation | 14 |
| Core Generation | 13 |
| Architecture / Codename | Raptor Lake / Golden Cove |
| Cores / Threads | 8P+16e/32 |
| Technology Node | 10 nm |
| Die Size | 257 mm² |
| Transistors | |
| Frequency | 3200-5800 MHz |
| Instructions | (80 KB / P-core) (32 KB + 48 KB) |
| TDP | 253 Watts (real TDP ~300 Watts) |
| Socket | Socket 1700 |
| Cache L2 | 1.25 MB / P-core |
| Cache L3 | 36 MB (shared) |
| Memory Type | DDR4-3200 or DDR5-4800 SDRAM |
| Memory Bandwidth | 75 GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 192 GB |
Raptor Lake Refresh / Golden Cove
14th gen is a minor refresh over 13th gen. Slightly higher clock speeds. Architecture and process node are identical. Ba...
📊 Benchmark Results (1)Raptor Lake Refresh / Golden Cove
14th gen is a minor refresh over 13th gen. Slightly higher clock speeds.
Architecture and process node are identical.
Back in the 1990's in the Pentium-1-era it would be just "hidden" refresh,
or a "minor chip revision", not even called a next-generation core.
But it's not just a 14th Gen Intel Core, but also a 14th-gen,
real Intel Architecture if counted since 8086, according to our view.
Making the chip at >300 watts TDP is little short of insane,
the TDPs has to go way way lower, probably under 100 watts by default,
including Turbo boost, and leave higher wattage exploration for over-clockers.
This TDP may causes both long-term instability *and* also noisy cooling for most average coolers.
This chip is essentially the equivalent of a factory-overclocked chip. (both the i7 and the i9)
Core i3 and i5 have more sane defaults, but still a far cry from Apple M4's 20 watts of TDP,
which is optimal for desktop users in our view.
1 result(s) recorded for this family.
Flagship: Intel(R) Core(TM) i9-14900K
ST score/GHz: 1,209 · MT score/Watt: 429
| Specification | Value |
|---|---|
| Introduced | 2023 |
| Arch Generation | 14 |
| Core Generation | 14 |
| Architecture / Codename | Raptor Lake Refresh / Golden Cove |
| Cores / Threads | 8P+16e/32 |
| Technology Node | 10 nm |
| Die Size | 257 mm² |
| Transistors | |
| Frequency | 3200-6000 MHz |
| Instructions | (80 KB / P-core) (32 KB + 48 KB) |
| TDP | 253 Watts (real TDP ~300 Watts) |
| Socket | Socket 1700 |
| Cache L2 | 1.25 MB / P-core |
| Cache L3 | 36 MB (shared) |
| Memory Type | DDR4-3200 or DDR5-4800 SDRAM |
| Memory Bandwidth | 75 GB/s |
| Memory Size Typical | 16-32 GB |
| Memory Size Max | 192 GB |