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P6 (Klamath and Deschutes) · Intel
the Pentium II. Revolutionary P6 architecture.
Super-scalar with multiple execution units, branch prediction and micro-code
to transform x86 to internal machine-code.
Much faster than the original Pentium, clock-for-clock on 32-bit code execution.
Speculative execution and out-of-order completion.
All modern processors are essentially based on this concept, so we can call all
modern CPUs as a Pentium II-descendats of sorts, at least in idea.
L2 cache works at half the CPU speed, so a 400 MHz chip had only a 200 MHz L2 cache.
L1 cache always works at full CPU speed, for all models.
Celeron, based on the Pentium II, had no L2 cache at all for early models, and only 128 KB
for later models; while Server-based Pentium II Xeon chips have had 1 MB or 2 MB full-speed L2.
8 result(s) recorded for this family.
Flagship: Intel Pentium II 400 MHz
ST score/GHz: 231 · MT score/Watt: 3.86
| Specification | Value |
|---|---|
| Introduced | 1997 |
| Arch Generation | 6 |
| Core Generation | pre-historic. |
| Architecture / Codename | P6 (Klamath and Deschutes) |
| Cores / Threads | 1/1 |
| Technology Node | 250 nm (250 for Deschutes and 350 nm for Klamath) |
| Die Size | 113 mm² (for Deschutes); and bigger for Klamath |
| Transistors | 7.5 million |
| Frequency | 233-450 MHz |
| Instructions | 16 KB / 16 KB |
| TDP | ~15-30? Watts |
| Socket | Slot 1 |
| Cache L2 | 512 KB; at half-speed. |
| Memory Type | SDRAM-100 |
| Memory Bandwidth | 1 GB/s |
| Memory Size Max | 4 GB (theoretical; or 64 GB in PAE mode) |
| Memory Size Typical | 64-128 MB |